Prior art, for example U.S. Pat. No. 3,798,621, generally discloses that in an IGFET circuit some of the devices can be fabricated as thin oxide elements and certain other elements fabricated as thick oxide elements with the latter serving as load devices. This type of implementation is an advantage in that increased densities are possible. That is, when IGFETs are intended to function as a load device and they are fabricated as thin oxide devices, then their channel length must be significantly increased in order to obtain the necessary value of impedance.
Nonetheless, in the actual implementation of this approach it is found that other problems are created. Namely, it is found that even though the use of thick oxide devices as load elements permits higher densities, albeit for certain applications an additional power supply is required, the problem of creating parasitic devices still exists. As is well known, conductor lines which are employed to provide a gate voltage to IGFET devices also transverses the upper thick oxide surface of the integrated circuit. Accordingly, in many instances the gate voltage conductive line is disposed over separated regions of a first conductivity type located in a substrate of opposite conductivity type. These and other regions are not intended to function as the source and drain elements of IGFET devices, but as electrically isolated regions. However, a sufficient voltage is capable of creating a space charge which will invert the semiconductor surface layer separating these regions so as to in effect create an IGFET device, known as a parasitic device.
Therefore, it is an object of the present invention to provide an IGFET circuit, in which oxide devices are employed as load elements and in which the possibility of creating parasitic devices is minimized.